Explore the Foundation of Computer Architecture System Organization, CPU Cycles & Data Flows

Computer Architecture describes the structure, organization, and behavioral design of computer hardware systems. It outlines how instructions are parsed, how memory is laid out, and how computer components communicate.

Most modern general-purpose computers are designed according to the Von Neumann Architecture, published in 1945 by mathematician John von Neumann.

Although often used interchangeably, Computer Architecture and Computer Organization focus on distinct layers of system design:

• Computer Architecture (Abstract): Describes the programmer-visible attributes of a system (Instruction Set Architecture - ISA). It defines data formats, registers, and memory addressing modes. *Example:* Implementing a new ISA instruction called `ADD`.
• Computer Organization (Physical): Describes how architectural specifications are physically implemented using gate-level circuits, wires, clock cycles, and control signals. *Example:* Deciding whether to implement the `ADD` operation using a Carry-Lookahead Adder or Ripple-Carry Adder.

The Central Processing Unit (CPU) is the "brain" of the computer, executing instructions and managing component coordination. It contains three main sub-components:

• Arithmetic Logic Unit (ALU): Performs basic mathematical calculations (addition, subtraction) and logical comparisons (AND, OR, NOT).
• Control Unit (CU): The supervisor. It decodes instructions fetched from memory and routes control signals directing the ALU, registers, and memory blocks.
• Registers: Tiny, ultra-fast memory storage locations located directly inside the CPU core.

In a computer system, memory is organized in a hierarchy to balance **speed** and **cost**. Registers are fast but small and expensive, while mechanical/solid-state hard drives are slow but massive and cheap.

I/O systems manage communication between the CPU/Memory and external peripheral devices (keyboards, monitors, network cards). There are three primary mechanisms for I/O operations:

• Programmed I/O (Polling): The CPU repeatedly queries the peripheral device to check if it has data ready. This keeps the CPU busy in a loop, wasting cycles.
• Interrupt-driven I/O: The peripheral device sends a hardware signal (Interrupt) to the CPU when it is ready. The CPU suspends its current work, runs an **Interrupt Service Routine (ISR)**, and resumes.
• Direct Memory Access (DMA): Used for high-speed transfers. A dedicated DMA controller copies blocks of data directly between peripheral devices and RAM, bypassing the CPU completely and notifying the CPU only when the transfer completes.

Computers use electrical switches (on/off states) to represent data. As a result, all characters, numbers, and symbols are stored using the Binary System (Base 2).

Negative integers are represented using Two's Complement representation. To convert a positive binary number to negative: invert all bits and add `1`.

Decimal: 5
Binary (8-bit): 00000101

Invert Bits: 11111010
Add 1:        11111011
Result (-5): 11111011

The CPU continuously executes a loop called the **Fetch-Decode-Execute Cycle** to process instructions:

1. Fetch: The CPU copies the instruction address from the Program Counter (PC) to the MAR, triggers a memory read, loads the instruction data into the MDR, and moves it to the Instruction Register (IR). The PC then increments.
2. Decode: The Control Unit (CU) parses the instruction code inside the IR to understand what operation (opcode) to run and identifies data operand locations.
3. Execute: The Control Unit routes control signals, the ALU performs arithmetic or logical operations, and results are written back to registers or RAM.

A Bus is a physical channel consisting of wires or copper tracks on a motherboard that transmits electronic signals between components. The main system bus consists of three sub-channels:

• Data Bus: Transmits actual data bits (bi-directional channel).
• Address Bus: Transmits memory locations to read/write (uni-directional channel pointing from CPU outward).
• Control Bus: Transmits command signals, synchronization clocks, and write/read indicators (bi-directional).

Evaluating processor speeds requires analyzing multiple execution variables:

• Clock Speed (Hz): The frequency of internal clock ticks per second. *Example:* A 3.2 GHz processor ticks 3.2 billion times per second.
• CPI (Cycles Per Instruction): The average number of clock cycles required to execute a single instruction.
• IPS (Instructions Per Second): Total instructions executed per second. Calculated as `Clock Speed / CPI`.

Modern computers implement optimization architectures to maximize throughput:

• Pipelining: An execution strategy that overlaps instruction execution stages, similar to an assembly line. While instruction 2 is being decoded, instruction 1 is executing, and instruction 3 is being fetched.
• RISC (Reduced Instruction Set Computer): Uses small, simplified instruction sets that execute in exactly one cycle, relying on compiler efficiency. *Example:* ARM processors.
• CISC (Complex Instruction Set Computer): Uses large, complex instructions that can perform multi-cycle tasks directly (e.g. copying directly from RAM to RAM). *Example:* Intel x86 processors.

Solve these architecture assembly analysis questions to consolidate your knowledge:

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